1. Basic characteristics

Ø  Support PCIe Gen3.0x8

Ø  Support various port and rate configuration modes such as 2x40G optical port, 2x10G optical port, 2x25G optical port, 4x10G optical port, 8x10G optical port and 8x1G optical/electrical port.

Ø  Support SRIOV, support 2 PF, each PF supports 126 VF.

Ø  Support RSS with a maximum of 256 queues.

Ø  Support sideband management; Support RMII/SMBus

Ø  Support SPI interface; Support external Flash

Ø  Package BGA 576, 25mm * 25mm

Ø  The commercial working temperature is 0℃ ~ 55℃, and the industrial working temperature is-40℃ ~ 85℃

2. Network characteristics

Ø  Support the unloading of data packets; Support IP/TCP and IP/UDP checksum unloading; TSO/GRO/TCO/RCO support.

Ø  Support VLAN tag insertion and stripping.

Ø  Support the filtering of data packets; Support packet filtering and redirection based on MAC/VLAN/TCP_SYN and quintuple.

Ø  Support flow control mechanism; Support FC/PFC

Ø  Support PTP；; Support IEEE 1588 v 2; Supports uploading data packets with timestamp.

Ø  Support virtual Ethernet bridge (VEB)

Ø  TSO and quintuple filtering based on VxLAN/NVRGE are supported.

Ø  Support QoS, and support the control of data flow according to the queue mechanism.

Ø  Supports jumbo frames up to 9564 bytes.

3. Security features (optional)

Ø  Support quotient secret SM2/SM3/SM4 algorithm.

Ø  Support international RSA2048/SHA256/AES algorithm.

Ø  Support TRNG/PUF

Ø  Support OpenSSL/TLS/IPSec uninstall acceleration.

Ø  High-speed hardware unloading of cryptographic algorithm

l  Symmetry algorithm: 40Gbps(SM4)

l  Hash algorithm: 40Gbps(SM3)

l  Asymmetric algorithm: 220,000 times per second (SM2 sign)

4. Programmable features (optional)

Ø  Built-in 4-core network protocol processor

Ø  Support L2-L4 network protocol programming.

5. superiority

Ø  40G high-performance network card chip, completely independent intellectual property rights.

Ø  It can be used in 2-port /4-port /8-port schemes, 10Gbps/25Gbps/40Gbps schemes, and is suitable for more application scenarios.

Ø  Reconfigurable cryptographic algorithm engine with 40G cryptographic acceleration capability.

Ø  It is programmable and can realize intelligent unloading of user network protocols.

Ø  Hardware offloads computing tasks, reduces CPU load and improves system operation efficiency.

6. Chip model